Browsing by Author "Vijaykrishnan, N."
Now showing items 1-20 of 24
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Analysis and solutions to issue queue process variation
Soundararajan, N.; Yanamandra, A.; Nicopoulos, Chrysostomos A.; Vijaykrishnan, N.; Sivasubramaniam, A.; Irwin, M. J. (2008)
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Article
Analysis of error recovery schemes for networks on chips
Murali, S.; Theocharides, Theocharis; Vijaykrishnan, N.; Irwin, M. J.; Benini, L.; De Micheli, G. (2005)
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ChipPower: An architecture-level leakage simulator
Tsai, Y. -F; Ankadi, A. H.; Vijaykrishnan, N.; Irwin, M. J.; Theocharides, Theocharis (2004)
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Design and analysis of an NoC architecture from performance, reliability and energy perspective
Kim, J.; Park, D.; Nicopoulos, Chrysostomos A.; Vijaykrishnan, N.; Das, C. R. (2005)
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Design of a dynamic priority-based fast path architecture for on-chip interconnects
Park, D.; Das, R.; Nicopoulos, Chrysostomos A.; Kim, J.; Vijaykrishnan, N.; Iyer, R.; Das, C. R. (2007)
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A distributed multi-point network interface for low-latency, deadlock-free on-chip interconnects
Park, D.; Nicopoulos, Chrysostomos A.; Kim, J.; Vijaykrishnan, N.; Das, C. R. (2006)
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Embedded hardware face detection
Theocharides, Theocharis; Link, G.; Vijaykrishnan, N.; Irwin, M. J.; Wolf, W. (2004)
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Evaluating alternative implementations for LDPC decoder check node function
Theocharides, Theocharis; Link, G.; Swankoski, E.; Vijaykrishnan, N.; Irwin, M. J.; Schmit, H. (2004)
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Book Chapter
An Exploration of Hardware Architectures for Face Detection
Theocharides, Theocharis; Nicopoulos, Chrysostomos A.; Irick, K.; Vijaykrishnan, N.; Irwin, M. J. (2006)
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Exploring fault-tolerant network-on-chip architectures
Park, D.; Nicopoulos, Chrysostomos A.; Kim, J.; Vijaykrishnan, N.; Das, C. R. (2006)
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A generic reconfigurable neural network architecture implemented as a network on chip
Theocharides, Theocharis; Link, G.; Vijaykrishnan, N.; Irwin, M. J.; Srikantam, V. (2004)
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Hardware Architectures for Face Detection
Irick, K.; Theocharides, Theocharis; Vijaykrishnan, N. (2006)
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Implementing LDPC decoding on network-on-chip
Theocharides, Theocharis; Link, G.; Vijaykrishnan, N.; Irwin, M. J. (2005)
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A low latency router supporting adaptivity for on-chip interconnects
Kim, J.; Park, D.; Theocharides, Theocharis; Vijaykrishnan, N.; Das, C. R. (2005)
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Book Chapter
Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip
Theocharides, Theocharis; Link, G. M.; Vijaykrishnan, N.; Irwin, M. J. (2005)
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A parallel architecture for hardware face detection
Theocharides, Theocharis; Vijaykrishnan, N.; Irwin, M. J. (2006)
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Performance Enhancement through Early Release and Buffer Optimization in Network-on-Chip Router Architectures
Kim, J.; Park, D.; Nicopoulos, Chrysostomos A.; Vijaykrishnan, N.; Das, C. R. (2006)
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Power-efficient implementation of turbo decoder in SDR system
Kang, B.; Vijaykrishnan, N.; Irwin, M. J.; Theocharides, Theocharis (2004)
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A Probabilistic Model for Soft-Error Rate Estimation in Combinational Logic
Kim, J. S.; Nicopoulos, Chrysostomos A.; Vijaykrishnan, N.; Xie, Y.; Lattanzi, E. (2004)
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Thermal-aware floorplanning using genetic algorithms
Hung, W. L.; Xie, Y.; Vijaykrishnan, N.; Addo-Quaye, C.; Theocharides, Theocharis; Irwin, M. J. (2005)